Semiconductor materials are typically made from atoms that share electrons with each other to exactly fill the "s" and "p" shells of each atom. The outer shells of such atoms may be occupied by as many as eight electrons. In silicon and germanium, each atom has four electrons in its outer shell. However, adjacent atoms share electrons so that each outer shell is occupied by eight electrons. Gallium arsenide (GaAs), another semiconductor, comprises gallium, having three outer shell electrons, and arsenide, having five outer shell electrons. The two types of atoms in GaAs share electrons to fill each outer shell with eight electrons.
In intrinsic or undoped semiconductors, the outer shell is filled and the material is actually insulating rather than semiconductive since no free carriers are available in the outer shell. However, there is always a lack or excess of electrons in real-world materials. An excess of electrons starts filling the next available shell, while a lack of electrons will leave a shell with vacancies. When a shell is not completely filled, the electrons are not tightly bound to the atom and can move from or to the non-filled shell, thus making the material conductive.
As atoms are brought together to form a semiconductive material, the electrons of each atom are acted on in such a way that the Pauli exclusion principle is obeyed, i.e., no two electrons in the material are allowed to have the same energy. This principle requires the existence of bands of allowed energies for electrons, with the bands typically separated by disallowed energy bands. The outermost band, which has the potential to be filled with electrons, is terminated by the valence band edge E.sub.v, and is separated from the next allowed energy by a disallowed energy band. The next allowed energy band, the conduction band, starts at the conduction band edge, E.sub.c. In ideal semiconductor materials (no impurities) electrons do not have energies between E.sub.v and E.sub.c, the disallowed energy band. The range of disallowed energies between E.sub.c and E.sub.v is termed the energy band gap, E.sub.g. FIG. 8 shows G(E), the density of allowed states as a function of energy for a semiconductor material.
In an n-type semiconductor, an excess of electrons exists, with the excess electrons having an energy at or above the conduction band edge E.sub.c. In p-type semiconductor material, electron vacancies exist, creating vacant energy states at or below the valence band edge E.sub.v. Electron vacancies are referred to as holes and can be thought of as having energies similar to electrons. Electron excesses or vacancies can be controlled quite precisely by doping to obtain the desired characteristics of a material.
The concept of discrete electrical "carriers" is commonly used in conceptualizing electric conduction in semiconductor materials. A carrier may be either an electron or a hole. Since holes are more abundant in p-type material than are electrons, holes are termed "majority carriers" in p-type material. Electrons in p-type material are termed "minority carriers." In n-type material, the situation is reversed--electrons are majority carriers and holes are minority carriers.
Statistical analysis is helpful in predicting and understanding the behavior of carriers in semiconductors. In particular, Fermi-Dirac statistics predict the distribution of electron energies and hole energies within n-type and p-type semiconductors. FIG. 5 illustrates the Fermi-Dirac distribution function, f.sub.D (E), for an undoped semiconductor material and gives the statistical probability of an electron having a particular energy E. The "Fermi Energy," E.sub.F, is that energy at which f.sub.D (E) equals one-half. The corresponding distribution function for holes is exactly the opposite that for electrons, or 1-f.sub.D (E).
E.sub.F is approximately midway between E.sub.c and E.sub.v in an intrinsic semiconductor (FIG. 5). E.sub.F changes as an intrinsic semiconductor is doped. In n-type semiconductors, E.sub.F is closer to the conductive band edge E.sub.c (FIG. 6). In p-type semiconductors, E.sub.F becomes closer to the valence band edge E.sub.v (FIG. 7).
Integrating the product of G(E) (FIG. 8) and f.sub.D (E) over energy E for p-type material (FIG. 7) yields a function n(E) of occupied states as shown in FIG. 9 for electrons in p-type material, and a function p(E) of occupied states as shown in FIG. 10 for holes in p-type material. A similar exercise may be performed for n-type material.
Based upon the probability function f.sub.D (E) and the Fermi level E.sub.F for an undoped semiconductor material (FIG. 5), it can be observed that virtually all energy states in the valence band will be occupied by electrons, and virtually all energy states in the conduction band will be occupied by holes. As the Fermi level E.sub.F increases (FIG. 6, n-type), the probability is higher that energy states within the conduction band will be occupied by electrons. As the Fermi level decreases (FIG. 7, p-type), the probability is higher that energy states within the valence band will be occupied by holes. In general, most allowable states above the Fermi level will be occupied by holes, and most allowable states below the Fermi level will be occupied by electrons.
In many semiconductor devices, circumstances arise wherein minority carriers are injected into specific regions of a semiconductor. For instance, electrons having energies in the conduction band are often injected into p-type regions. As can be seen in FIG. 7, the probability of an electron having such an energy is very low in p-type material, and the electron will often "recombine" with a hole in the conduction band--the electron will fall to a lower energy state to fill the hole. However, recombination occurs over time--while many electrons recombine quickly, others can travel a significant distance within the p-type material before recombining. Thus, at any time, a small but significant number of injected minority carriers are likely to be present in the p-type material.
CMOS integrated circuits are particularly sensitive to the injection and continued presence of minority carriers in the substrate material. Minority carrier injection into the bulk substrate tends to induce latchup or to discharge dynamic storage nodes in dynamic memory circuits.
Latchup is a well-known phenomenon in CMOS circuits, and significant effort is expended during the design of CMOS structures to eliminate latchup. A pair of undesirable parasitic bipolar transistors, inherent in the basic CMOS structure, facilitates latchup. If one of the parasitic transistors becomes forward biased, an internal feedback path will permanently latch both parasitic transistors in the forward-biased condition--usually creating a short between a voltage supply and ground. The latchup condition can be eliminated only by removing power from the circuit.
The tendency of a CMOS structure to behave in this way depends upon the gain of the parasitic transistors, with higher transistor gain making latchup more likely. The gain of CMOS parasitic bipolar transistors is, in turn, determined by the number of minority carriers present within the circuit's bulk substrate. A greater number of injected minority carriers increases parasitic transistor gain and, therefore, increases the likelihood of latchup.
Dynamic storage nodes may also be affected by injected minority carriers. DRAM charged storage capacitors in CMOS are accessed by n-channel MOS field effect transistors. However, an n.sup.+ region of such a transistor, positively charged by a storage capacitor, will tend to attract substrate minority carriers (electrons) from the underlying p-type material. These electrons, when accepted by the n.sup.+ region and capacitor, can discharge the capacitor to an unacceptable level, effectively removing a positive charge from the storage capacitor. Such a result is obviously harmful to the proper operation of a DRAM circuit.
Minority carriers, as mentioned above, naturally tend to recombine with majority carriers present in the substrate. However, in typical CMOS circuits, a significant number of minority carriers avoid recombination, often leading to latchup or discharging of dynamic storage nodes as described above. Prior attempts to reduce the number of minority carriers have been directed toward attacting such carriers to appropriately charged "guard rings."
FIGS. 1 and 2 illustrate prior art CMOS structures utilizing guard rings to attract and draw away minority carriers. Both figures illustrate similar structures, and features common to both figures are designated with identical reference numerals.
FIG. 1 illustrates a portion of a typical CMOS structure 10 including one p-channel MOS field effect transistor 12 and two n-channel MOS field effect transistors 14 and 16. Guard rings 20 and 22 separate the transistors. Separating areas 21 of field oxide are located between guard rings and transistors.
Each transistor has two active source and drain areas, with p-channel devices having p.sup.+ active areas and the n-channel devices having n.sup.+ active areas. Active areas of a transistor are diffused into a substrate well of complementary semiconductor material and spaced such that the complementary semiconductor material separates the two active areas. It is of course possible to use the bulk substrate as the well for transistors of complementary material to the bulk substrate. In this document, "substrate" by itself refers to either a substrate well or the bulk substrate. The channel area between each active area pair is covered by a thin layer of oxide over which a conductively doped polysilicon electrode, the gate, is applied. The active areas of transistors 10, 12, and 14 are designated with the suffix "a" and the gate of each transistor is designated with the suffix "b". The substrate well material into which the active areas are diffused is designated with the suffix "c". A bulk substrate 23 of p.sup.- material underlies the substrate wells. Accordingly, the substrate is comprised of a bulk substrate and substrate wells.
Guard rings 20 and 22 are diffused in the substrate well material between adjacent transistors. Each guard ring comprises an n.sup.+ area, designated with the suffix "a"; a p.sup.+ area, designated with the suffix "b"; and a separating area of field oxide, designated with the suffix "c". Each n.sup.+ area 20a and 22a is connected to V.sub.cc, typically the highest voltage supplied to the chip. Each p.sup.+ area 20b and 22b is connected to V.sub.ss, typically the lowest voltage used within the chip.
When a positive voltage (with respect to the voltage of the substrate) is applied to the gate of an n-channel transistor such as transistor 14, electrons in p-well 14c are attracted toward gate 14b and accumulate in the channel. This accumulation of electrons creates an inversion layer beneath gate 14b--the p-type substrate well material of the channel is electrically and temporarily changed to n-type material. A conduction path for majority carriers (electrons) is thus created between active areas 14a through the now n-type channel.
In the FIG. 1 illustration, electrons are majority carriers in n.sup.+ active areas 14a and 16a of n-channel transistors 14 and 16. However, conditions do arise whereby some electron carriers are injected into the underlying substrate wells 14c and 16c and bulk substrate 23, outside of the channel, where they are classified as minority carriers. Such injected electrons seek to achieve a lower energy state by recombining with complimentary holes in the p material.
However, minority carrier lifetime (time to recombine) within the substrate is long enough that circuit techniques are used to collect minority carriers. Guard rings 20 and 22 are fabricated between transistors to attract and draw away those electrons which avoid recombination. The paths of injected minority carrier electrons are illustrated by dashed lines 24, 25, and 26 in FIG. 1. Guard rings 20 and 22 have positively charged n.sup.+ areas 20a and 22a which tend to attract minority carrier electrons from the substrate. For example, an electron whose path is illustrated by dashed line 24 is attracted to n.sup.+ guard ring area 20a, and an electron whose path is illustrated by dashed line 25 is attracted to n.sup.+ guard ring area 22a. Other electrons, such as those following path 26, impinge on and are collected by n.sup.+ active areas of adjacent transistors, in this case active area 16a, when those active areas are at a positive voltage. If the positive voltage is created by a positive charge at a dynamic storage node, such a positive charge will eventually be depleted, resulting in loss of the data stored at the dynamic storage node.
A modified construction intended to increase the likelihood of minority carriers being received by guard rings is illustrated in FIG. 2. Here, an implant layer 28 is provided beneath but adjacent the source/drain active areas of the transistors. Implant layer 28 is comprised of silicon dioxide which acts as a barrier. The barrier causes electrons to reflect back into the local substrate well area from which they were originally injected and eventually into adjacent rings.
Prior attempts to reduce the number of minority carriers in a semiconductor have principally focused on directing those minority carriers toward collection areas such as guard rings. This invention, however, focuses on reducing the number and effects of detrimental minority carrier substrate injection by promoting recombination of minority carriers near the source of injection rather than collection of minority carriers at a guard ring.